1. Field of the Invention
This invention relates to a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device for accurately interrupting an internal column strobe signal corresponding to an input command in a high and a low frequencies, when interrupt commands such as read and burst stop commands are received in the middle of a burst length set in a mode set register MRS in operation of the synchronous semiconductor memory device.
2. Description of the Related Art
FIG. 1 shows a block diagram of a synchronous semiconductor memory device which generates an internal column strobe signal in the prior art. The synchronous semiconductor memory device includes a clock buffer circuit 10, an internal clock generation circuit 20, a command decoder circuit 30, a burst generation control circuit 40, a burst signal generation circuit 50 and an internal column strobe generation circuit 60. The clock buffer circuit 10 receives a clock enable signal cke and an external clock signal clk to generate an internal clock signal clkp2z. The internal clock generation circuit 20 receives the internal clock signal clkp2z generated from the clock buffer circuit 10 to generate another internal clock signal clkp4z.
The command decoder circuit 30 receives the internal clock signal clkp4z from the internal clock generation circuit 20 and external column strobe signals such as a chip select bar signal csb, a RAS (Row Address Strobe) bar signal rasb, a CAS (Column Address Strobe) bar signal casb, and a write enable bar signal web to generate internal command signals caspz, pcgpz and bstmpz.
The burst generation control circuit 40 receives input signals refx, cast10z&lt;0:3&gt;, eatz&lt;10&gt; and eatz&lt;13:14&gt; and the internal command signals pcgpz and bstmpz from the command decoder circuit 30 to generate a burst generation control signal bstm10pz. Herein, the input signal refx is a signal which is in a low state, only when the synchronous DRAM (SDRAM) is a refresh mode.
The burst signal generation circuit 50 receives a power-up signal pwrupz, the internal command signal caspz, the burst generation control signal bstm10pz, the input signal refx and a burst length stop signal yblendzp to generate a burst signal ybstz. Herein, the burst length stop signal yblendzp becomes disabled in a low state, when the burst length is stopped.
The internal column strobe generation circuit 60 receives the internal clock signal clkp4z and the burst signal ybstz to generate an internal column strobe signal icaspz. FIG. 2 is a circuit diagram of the internal column strobe generation circuit 60. As shown in FIG. 2, the internal column strobe generation circuit 60 includes a NAND gate ND1 for receiving the internal clock signal clkp4z and the burst signal ybstz, inverters IN1 and IV2 connected in series between an output of the NAND gate ND1 and a node Nd1, inverters IV3 and IV4 connected in series between the node Nd1 and a node Nd2, a NAND gate ND2 for receiving output signals of the inverters IN2 and IV4 at the nodes Nd1 and Nd2 and inverters IN5 and IV6 connected in series to an output of the NAND gate ND2 and for generating the internal column strobe signal icasp6z.
The operation of the internal strobe generation circuit 60 will be described with reference to the timing diagram of FIG. 3. First, the internal clock signal clkp4z of high state is generated with synchronization to the external clock signal clk, the command decoder circuit 30 receives the external command signals csb, rasb, casb, web) and the internal clock signal clkp4z and generates the external column strobe signal caspz by the internal clock signal clkp4z. After the external column strobe signal caspz is enabled, the burst signal generation circuit 50 which receives the external column strobe signal caspz generates the burst signal ybstz of high state.
The internal column strobe generation circuit 60 which receives the burst signal ybstz and the internal clock signal clkp4z generates the internal column strobe signal icasp6z with synchronization to the internal clock signal clkp4z during the enable interval of the burst signal ybstz, i.e. the high state of the burst signal ybstz.
However, the prior synchronous DRAM including the internal column strobe generation circuit 60 having the above construction immediately interrupts the internal column strobe generation circuit to generate the internal column strobe signal which is corresponding to the input command in a low frequency, if the interrupt commands such as read, write and burst stop commands are received in the middle of the burst length set through the mode register set MRS in operation of the SDRAM. Therefore, the time that the burst signal ybstz becomes in a low state in high frequency is slow so that the internal column strobe signal is generated after the burst stop.
FIG. 4 is a timing diagram illustrating the above problem. Referring to FIG. 4, it is noted that the internal column strobe signal icasp6z is also generated after the burst stop in high frequency. From the timing diagram of FIG. 4, because the signal indicating the burst length stop is disabled in a low state and then the burst signal ybstz is disabled after the lapse of a constant time, the internal column strobe signal icasp6z of one clock is generated, after burst stop. Accordingly, the undesired internal column strobe signal icasp6z causes the malfunction of the SDRAM, thereby occurring the current consumption.
Besides, in the prior SDRAM, only the burst signal ybstz interrupts the internal column strobe signal icasp6z. According to this, the construction of the burst signal generation circuit which generate the burst signal in accordance with the interrupt commands becomes complicate and it is difficult to control the operation of the SDRAM with the interrupt command.